1. Field of the Invention
The present invention relates to a non-volatile memory device, such as a flash memory, or the like, and more particularly, to a non-volatile memory device whereby over-erasing is prevented and erasing time is shortened.
2. Description of the Related Art
Electrically rewritable non-volatile memory devices, such as a flash memories or EEPROMs, are capable of storing data in an unpowered state, and are widely used in portable telephones, portable information terminals, and the like. Flash memories, in particular, have been developed to high memory capacities, and erasing is carried out in high-capacity memory block units.
A memory cell in a non-volatile memory generally comprises: a control gate connected to a word line; a drain connected to a bit line; and a source connected to a source line. A programming operation (writing data 0) is carried out by applying a high voltage to the control gate and drain so that the memory cell transistor is switched conductive, and by setting the source to a low voltage so as to injecting the electrons passing along the channel to a floating gate. Supplying a prescribed voltage to the memory cell in order to carry out this program operation is known as applying "programming stress". When a program operation is executed, the memory cell transistor has a higher threshold voltage.
Moreover, in the erasing operation, the electrons are drawn away from the floating gate by setting the control gate to a low voltage or negative voltage, setting the drain to a floating state, and setting the source to a high voltage.
This operation of applying a prescribed voltage to the memory cell is known as applying "erasing stress". When an erasing operation is carried out, the memory cell transistor has a low threshold voltage.
In the read-out operation, by controlling the word line to an intermediate voltage between the threshold voltages of the programmed and erased transistors, the memory cell transistors in a programmed state are switched OFF (non-conductive), whilst the memory cell transistors in an erased state are switched ON (conductive), and this presence or absence of current according to the OFF or ON state of the transistors is detected by means of the bit line.
In the erasing operation, after the aforementioned erasing stress has been applied for a prescribed unit time, the memory cell being erased is read out to check (verify) if its threshold voltage is less than the erasure verification level. By repeating the operations of applying this erasing stress and verifying erasure, a suitable erasing operation is performed. In a flash memory using a non-volatile memory, erasing is performed for a whole memory block comprising a plurality of memory cells, in one batch.
In the aforementioned erasing operation, if an erasing stress is applied more times than necessary, the threshold voltage of the memory cell transistors will become negative, meaning that even if the word line is in an unselected state (L level), the memory cell connected thereto will be switched ON, which is undesirable. This state is known as "over-erasing", and must be avoided in the erasing operation.
On the other hand, as memory capacity increases, there is a tendency towards increased variation in the number of applications of, and time period of, erasing stress which is required for each memory cell or each memory block. In general, an erasing operation is carried out by applying an erasing stress to a plurality of memory cells in one batch. Therefore, if erasure has been completed in one portion of the memory cells but it has not been completed in the other memory cells, the erasing stress will still be applied equally to the memory cells which have been completely erased. Consequently, a portion of the memory cells will be "over-erased". The greater the number of memory cells to which an erasing stress is applied in one batch, the greater the variation in the number of erasing stress applications required, and hence the greater the probability of over-erasing.
In order to avoid these-over-erasing problems, conventionally, a memory region is divided into a plurality of memory blocks, and the operations of applying an erasing stress and verifying erasure are repeated for each memory block. By reducing the number of memory cells which are erased in a single operation, it is possible to suppress variation in the threshold voltages of memory cells after application of the erasing stress, thereby avoiding the problems of over-erasing.
However, if a method is adopted whereby the operations of applying erasing stress and verifying erasure are repeated for each memory block, individually, then the time taken to erase all of a plurality of memory blocks will become long. In flash memories, in particular, where high memory capacity is being developed, this lengthening of the erasing time is a problem which must be resolved.